Download System-level Test and Validation of Hardware/Software by Matteo Sonza Reorda,Zebo Peng,Massimo Violante PDF

By Matteo Sonza Reorda,Zebo Peng,Massimo Violante

New production applied sciences have made attainable the combination of complete structures on a unmarried chip. This new layout paradigm, termed system-on-chip (SOC), including its linked production difficulties, represents a true problem for designers.

SOC is usually reshaping methods to check and validation actions. those are starting to migrate from the normal register-transfer or gate degrees of abstraction to the procedure point. formerly, try out and validation haven't been supported via system-level layout instruments so designers have lacked the infrastructure to take advantage of all of the merits stemming from the adoption of the method point of abstraction. study efforts are already addressing this issue.

This monograph presents a state of the art evaluation of the present validation and try out innovations via overlaying all elements of the topic including:

  • modeling of insects and defects;

  • stimulus new release for validation and try reasons (including timing errors;

  • design for testability.

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